Abstract: 

The continuing trend in applications for ever increasing functionality, performance and integration is leading to designs with power dissipation in the order of hundreds of Watts. Reducing on-chip power consumption has become a critical challenge today and the traditional trade-offs between performance and area are now being compounded by the addition of power into the equation. Therefore, the power architecture of System-on-Chips (SoCs) has become increasingly complex with multiple power domains and voltage/power islands supporting several states of activity. With these complexities it becomes significantly important to verify the implementation of power architecture and power gating cells so that any Silicon issues could be averted upfront. In parallel, there is also a need to support the lacking behavior of many third-party implementation tools in understanding and retaining the power/ground (PG) connectivity coming from RTL. To cater above requisites, power formats like IEEE-1801 Unified Power Format (UPF) and Common Power Format (CPF) are used in order to deploy signoff’s right from RTL till GDSII.

The sign-off checks are performed to ensure that the SoC is free from the following issues, which could lead to functionality failure or in most cases, silicon failure:

a. Whether any signal is traversing from one power domain to another power domain

b. Whether any signal is traversing from one voltage island to another voltage island

c. Whether any buffering is present at the analog nets

d. Whether a gate of a MOS device (for < 90nm) is directly connected to power / ground net

e. Whether a control signal of power switch is driven by a power domain which is dependent on the state of power switch itself.